![]() Major improvements to the Blackbox RTL import flow in to Vitis Model Composer.Enhanced Window Processing Block to target URAM resource.Enhancement to HLS Kernel block to support extended templatized parameters.Margin can be specified through kernel code.Specifying size through GUI or kernel code supported.sync, async, cyclic buffer_1d are supported.Added buffer_1d support as Early Access.Upshift center tap parameter added for FIR Halfband interpolator window and stream blocks.Interpolate Polyphase (TP_PARA_INTERP_POLY) parameter added to Halfband Interpolate block.Decimate Polyphase (TP_PARA_DECI_POLY) parameter added to Halfband Decimator block. ![]()
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